TFTs (Thin Film Transistors) are widely used as basic electronic devices for controlling pixels of a TFT liquid crystal display (LCD). For this application, TFT units are formed on a glass substrate. Since the glass substrate is generally not heat resistant, the process for producing TFTs on the LCD glass plate should be a low-temperature manufacturing process. FIG. 1 is a schematic cross-sectional view illustrating the structure of a typical TFT, and the process for forming such TFT. First, a gate electrode 105 is formed on a glass substrate 100, and the substrate 100 and the gate electrode 105 are then covered with a gate insulator 110. Subsequently, an amorphous silicon layer 115 is formed on the gate insulator 110 to be used as a channel layer. Finally, source/drain regions 120 are formed on the amorphous silicon layer 115.
Since the glass substrate 100 is not able to sustain high temperature during the producing process, only the amorphous silicon layer 115 other than a polysilicon layer is formed in the process mentioned above. It is known that the TFT having the amorphous silicon layer 115 has electrical properties inferior to a TFT having the polysilicon layer. Recently, a TFT having a polysilicon layer was produced by a laser annealing procedure at a relatively low temperature. The laser annealing procedure is well known to those skilled in the art and will not be described in details herein. The laser annealing procedure improves electrical properties of TFT transistors and facilitates direct formation of TFTs on a glass substrate. FIG. 2 illustrates a typical low-temperature polysilicon thin film transistor (LTPS-TFT). The LTPS-TFT in FIG. 2 comprises a polysilicon layer 200, N-type regions 205, a gate insulator 210, an interlayer dielectric layer 215, a gate electrode 220 and source/drain conductive lines 225, which are all formed on a glass substrate (not shown). Since these two N-type regions 205 are heavily doped and has a short distance from the gate electrode 220, a so-called “hot electron effect” which impairs stability of the LTPS-TFT is rendered.
In order to minimize the hot electron effect, an LTPS-TFT having an LDD (lightly doped drain) structure was developed. Two examples of the processes for producing such LTPS-TFT are illustrated with reference to FIGS. 3(a) to 3(e) and FIGS. 4(a) to 4(c), respectively. In FIG. 3(a), a polysilicon layer 300 is formed on a glass substrate (not shown) by a laser annealing procedure, and then a gate insulator 310 is formed on the polysilicon layer 300. Then, a gate electrode 320 is formed on the gate insulator 310, and N-type regions 305 are formed by a first ion doping procedure with the gate electrode 320 serving as a mask. Then, the gate insulator 310 and the gate electrode 320 are covered with a dielectric layer 330, as can be seen in FIG. 3(b). In FIG. 3(c), a sidewall or spacer 335 is formed beside the gate electrode 320. Then, as shown in FIG. 3(d), LDD (lightly doped drain) regions 340 are formed just below the surface of the polysilicon layer 300 by a second ion doping procedure with the gate electrode 320 and the sidewall/spacer 335 serving as a mask. Meanwhile, heavily doped N-type regions 306 are formed, and the LDD regions 340 are disposed between and in the vicinity of these two heavily doped N-type regions 306. Finally, an interlayer dielectric layer 315 and source/drain conductive lines 325 are formed in sequence, thereby forming the LTPS-TFT having an LDD structure shown in FIG. 3(e).
FIGS. 4(a) to 4(c) illustrates another process for producing the LTPS-TFT having LDD structures. In FIG. 4(a), a polysilicon layer 400 is formed on a glass substrate (not shown), and N-type regions 405 are formed on the polysilicon layer 400 by a first ion doping procedure with a photoresist 430 serving as a mask. Then, as shown in FIG. 4(b), the photoresist 430 is removed, and a gate insulator 410 is formed on the polysilicon layer 400. A gate electrode 420 is then formed on the gate insulator 410 at a position where the photoresist 430 was formed previously, but has cross-sectional area less than that of the photoresist 430 formed in the previous step shown in FIG. 4(a). LDD regions 440 are then formed just below the surface of the polysilicon layer 400 by a second ion doping procedure. Meanwhile, the heavily doped N-type regions 406 are formed. Finally, an interlayer dielectric layer 415 and source/drain conductive lines 425 are formed in sequence, thereby forming the LTPS-TFT having an LDD structure shown in FIG. 4(c).
Since the LTPS-TFT of FIG. 3(e) or FIG. 4(c) has LDD regions just below the surface of the polysilicon layer, such structure is referred as a surface LDD structure. The ion doping procedures mentioned above can be ion implantation procedures and/or ion shower procedures. The dopants for the ion implantation procedure or the ion shower procedure can be P, As, PHx or AsHx. The LTPS-TFT having the LDD structures as shown in FIG. 3(e) or FIG. 4(c) is also referred as a gate-drain overlapped LDD (GO-LD). It is known that the valence distribution of dopants for an ion implantation procedure is controlled relatively precisely compared to an ion shower procedure. Since the doped drain region comprises lightly doped regions in addition to heavily doped regions, the electric field intensity in the vicinity of the drain regions is slightly diminished and thus the influence of the hot electron effect is reduced. However, the electric field intensity in the vicinity of the drain regions is still very strong so as to adversely affect movement of electrons in the channel between the two LDD regions. When electrons flow through the channel and in the vicinity of the LDD regions, the energy of the electrons is very high due to the strong electric field intensity in the vicinity of the LDD regions. Therefore, two undesirable effects occur. In view of the first effect, the silicon-hydrogen bonds at the interface between the gate insulator and the polysilicon layer may be cut off by such high energy so as to increase the interface state and result in inferior sub-threshold swing. In view of the second effect, electrons may be scattered into the gate insulator to generate an oxide trap state so as to cause a change of the threshold voltage and abnormal operations of electronic devices.
With the increasing demand of the quality of a low temperature polysilicon liquid crystal display (LCD), it is required to increase the size and resolution of the display. Furthermore, the circuits to be incorporated into the display are more complicated than ever. For example, the circuitry involves in one or more shift registers, level shifters, digital-to-analog converters (DACs), dynamic random access memories (DRAMs), and even operation amplifiers (OP). Accordingly, it is predicted that the channels of transistors will become narrower and narrower, and electric field intensities at the channels will be stronger and stronger. The above-described effects will be even significant.